Prac4_Part1a_2012 Project Status (03/19/2012 - 16:50:38)
Project File: Prac4_Part1a_2012.xise Parser Errors: No Errors
Module Name: Prac4_Part1a_2012 Implementation State: Programming File Generated
Target Device: xc3s500e-5fg320
  • Errors:
No Errors
Product Version:ISE 13.4
  • Warnings:
52 Warnings (52 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 147 9,312 1%  
Number of 4 input LUTs 139 9,312 1%  
Number of occupied Slices 114 4,656 2%  
    Number of Slices containing only related logic 114 114 100%  
    Number of Slices containing unrelated logic 0 114 0%  
Total Number of 4 input LUTs 167 9,312 1%  
    Number used as logic 139      
    Number used as a route-thru 28      
Number of bonded IOBs 15 232 6%  
Number of BUFGMUXs 4 24 16%  
Average Fanout of Non-Clock Nets 2.62      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon 19. Mar 16:49:03 2012052 Warnings (52 new)0
Translation ReportCurrentMon 19. Mar 16:49:17 2012000
Map ReportCurrentMon 19. Mar 16:49:26 2012002 Infos (2 new)
Place and Route ReportCurrentMon 19. Mar 16:50:12 2012003 Infos (3 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon 19. Mar 16:50:21 2012006 Infos (6 new)
Bitgen ReportCurrentMon 19. Mar 16:50:33 2012000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrentMon 19. Mar 16:50:33 2012

Date Generated: 03/19/2012 - 16:50:40